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the mc14lc5447 is a silicon gate hcmos ic designed to demodulate bell 202 and v.23 1200baud fsk asynchronous data. the primary application for this device is in products that will be used to receive and display the calling number, or message waiting indicator sent to subscribers from participating central office facilities of the public switched network. the device also contains a carrier detect circuit and ring detector which may be used to power up the device. applications for this device include adjunct boxes, answering machines, feature phones, fax machines, and computer interface products. the mc14lc5447 offers the following performance features. ? ring detector onchip ? ring detect output for mcu interrupt ? powerdown mode, less than 1 m a ? single supply: + 3.5 to + 6.0 v ? pin selectable clock frequencies: 3.68 mhz, 3.58 mhz, or 455 khz ? two stage powerup for power management control ? demodulates bell 202 and v.23 block diagram + osc out clksin rdo cdo dor doc osc in demod v ag v ss pwrup rt rdi2 rdi1 ring tip v dd no connect (5) ring detect circuit valid data detect internal power up clock gen bpf 1 2 3 4 6 7 10 9 14 15 13 12 11 16 8 this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice. order this document by mc14lc5447/d semiconductor technical data p suffix plastic dip case 648 dw suffix sog package case 751g ordering information MC14LC5447P plastic dip mc14lc5447dw sog package 16 1 16 1 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 rdo cdo dor doc v dd osc out osc in clksin rdi2 rdi1 ri ti v ss pwrup rt nc pin assignment nc = no connection ? motorola, inc. 1996 rev 0 7/96 a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc14lc5447 motorola 2 absolute maximum ratings (voltages referenced to gnd, except where noted) rating symbol value unit dc supply voltage v dd 0.5 to + 6.0 v input voltage, all pins v in 0.5 to v dd + 0.5 v dc current drain per pin i 10 ma power dissipation p d 20 mw operating temperature range t a 0 to + 70 c storage temperature range t stg 40 to + 150 c electrical characteristics (all polarities referenced to v ss = 0 v, v dd = + 5 v 10%, unless otherwise noted, t a = 0 to + 70 c) parameter symbol min typ max unit dc supply voltage v dd 3.5 5 6 v supply current (all output pins unloaded) (see figure 1) rt = 0, pwrup = 1, xtal = 3.58 mhz i dd e 2.4 3 ma supply current (all output pins unloaded) (see figure 1) pwrup = 0, rt = don't care, xtal = 3.58 mhz i dd e 4.0 5.5 ma standby current (all output pins unloaded) (see figure 1) rt = 1, pwrup = 1 i stby e e 1 m a input voltage 0 level (clksin, osc in ) v il e e v dd x 0.3 v input voltage 1 level (clksin, osc in ) v ih v dd x 0.7 e e v output voltage high: v dd = 5 v (dor, doc, osc out ) i oh = 40 m a i oh 1 m a v oh 2.4 4.95 e e v output voltage low: v dd = 5 v (dor, doc, osc out ) i ol = 1.6 ma i ol 1 m a v ol e e 0.4 0.05 v input leakage current (osc in , clksin, pwrup , rt , rdi1, and rdi2) i in e e 1 m a output voltage low: v dd = 5 v (rdo , rt , cdo ) i ol = 2.0 ma v ol e e 0.4 v input threshold voltage positive going: v dd = 5 v (rdi1, rt , pwrup ) (see figure 3) v t+ 2.5 2.75 3.0 v input threshold voltage negative going: v dd = 5 v (rdi1, rt , pwrup ) (see figure 3) v t 2.0 2.3 2.6 v rdi2 threshold r d2 v t 1.0 1.1 1.2 v tip/ring input dc resistance r in e 250 e k w analog characteristics (v dd = + 5 v, t a = + 25 c, unless otherwise noted, 0 dbm = 0.7746 vrms @ 600 w ) characteristic min typ max unit input sensitivity: tip and ring (pins 1 and 2, v dd = + 5 v) 40 45 e dbm bandpass filter (bpf) frequency response (relative to 1700 hz @ 0 dbm) 60 hz 500 hz 2700 hz 3300 hz e e e e 64 4 3 34 e e e e db carrier detect sensitivity e 48 e dbm this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields. however, it is advised that normal precautions be taken to avoid applica- tions of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss or v dd ). a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc14lc5447 motorol a 3 switching characteristics (v dd = + 5 v, c l = 50 pf, t a = + 25 c) description symbol min typ max unit osc startup (clksin = 1; 3.579 mhz xtal) t dosc e 2 e ms powerup low to fsk (setup time) t supd 15 e e ms carrier detect acquisition time t daq e 14 e ms end of data to carrier detect high t dch 8 e e ms timing diagram osc pwrup rt doc ri 2 seconds 0.5 second 0.5 second data 0101 1 cooked data raw data clock 3.58 mhz, 3.6864 mhz, or 455 khz t dosc t dch t daq t supd dor rdo cdo threshold to keep part on a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc14lc5447 motorola 4 12 rdo 13 cdo 14 dor 3.579 mhz 15 doc 11 clksin 10 osc in 9 osc out pwrup 7 rt 6 nc 5 rdi1 3 ri 2 ti 1 30 pf rdi2 4 open v dd 0.1 m f 30 pf 10 m w 16 8 rt pwrup i dd osc in 111 m a max disable 0 1 2.4 ma typ enable x 0 6.2 ma typ enable v dd figure 1. i dd test circuit pin descriptions ti tip input (pin 1) this input pin is normally connected to the tip side of the twisted pair. it is internally biased to 1/2 supply voltage when the device is in the powerup mode. this pin must be dc iso- lated from the line. ri ring input (pin 2) this input is normally connected to the ring side of the twisted pair. it is internally biased to 1/2 supply voltage when the device is in the powerup mode. this pin must be dc iso- lated from the line. rdi1 ring detect input 1 (pin 3) this input is normally coupled to one of the twisted pair wires through an attenuating network. it detects energy on the line and enables the oscillator and precision ring detec- tion circuitry. rdi2 ring detect input 2 (pin 4) this input to the precision ring detection circuit is normally coupled to one of the twisted pair wires through an atte- nuating network. a valid ring signal as determined from this input sends the rdo (pin 12) to a logic 0. rt ring time (pin 6) an rc network may be connected to this pin. the rc time constant is chosen to hold this pin voltage below 2.2 v be- tween the peaks of the ringing signal. rt is an internal powerup control and activates only the circuitry necessary to determine if the incoming ring is valid. pwrup power up (pin 7) a logic 0 on the pwrup input causes the device to be in the active mode ready to demodulate incoming data. a logic 1 on this pin causes the device to be in the standby mode, if the rt input pin is at a logic 1. this pin may be con- trolled by rdo and cdo for auto powerup operation. for other applications, this pin may be controlled externally. v ss ground (pin 8) ground return pin is typically connected to the system ground. osc out oscillator output (pin 9) this pin will have either a crystal or a ceramic resonator tied to it with the other end connected to osc in . osc in oscillator input (pin 10) this pin will have either a crystal or a ceramic resonator tied to it with the other end connected to osc out . osc in may also be driven directly from an appropriate external source. clksin clock select input (pin 11) a logic 1 on this input configures the device to accept ei- ther a 3.579 mhz or 3.6864 mhz crystal. a logic 0 on this pin configures the part to operate with a 455 khz resonator. for crystal and resonator specifications see table 1. rdo ring detect out (pin 12) this opendrain output goes low when a valid ringing signal is detected. rdo remains low as long as the ringing signal remains valid. this signal can be used for auto power up, when connected to pin 7. cdo carrier detect output (pin 13) when low, this open drain output indicates that a valid carrier is present on the line. cdo remains low as long as the carrier remains valid. an 8 ms hysteresis is built in to allow for a momentary drop out of the carrier. cdo may be used in the auto powerup configuration when connected to pwrup . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc14lc5447 motorol a 5 dor data out raw (pin 14) this pin presents the output of the demodulator whenever cdo is low. this data stream includes the alternate 1 and 0 pattern, and the 150 ms of marking, which precedes the data. at all other times, dor is held high. doc data out cooked (pin 15) this output presents the output of the demodulator when- ever cdo is low, and when an internal validation sequence has been successfully passed. the output does not include the alternate 1 and 0 pattern. at all other times, doc is held high. v dd positive power supply (pin 16) the digital supply pin, which is connected to the positive side of the power supply. applications information the mc14lc5447 has been designed to be one of the main functional blocks in products targeted for the class (custom local area signaling service) market. class is a set of subscriber features now being presented to the con- sumer by the rbocs (regional bell operating companies) and independent telcos. among class features, such as distinctive ringing and selective call forwarding, the subscrib- er will also have available a service known as calling num- ber delivery (cnd) and message waiting. with these services, a subscriber will have the ability to display at a mini- mum, a message containing the phone number of the calling party, the date, and the time. a message containing only this information is known as a single format message, as shown in figure 9. an extended message, known as multiple format message, can contain additional information as shown in figure 10. the interface should be arranged to allow simplex data transmission from the terminating central office, to the cpe (customer premises equipment), only when the cpe is in an onhook state. the data will be transmitted in the silent peri- od between the first and second power ring after a voice path has been established. the data signaling interface should conform to bell 202, which is described as follows: ? analog, phase coherent, frequency shift keying ? logical 1 (mark) = 1200 12 hz ? logical 0 (space) = 2200 22 hz ? transmission rate = 1200 bps ? application of data = serial, binary, asynchronous the transmission level from the terminating c.o. will be 13.5 dbm 1.0. the expected worst case attenuation through the loop is expected to be 20 db. the receiver therefore, should have a sensitivity of approximately 34.5 dbm to handle the worst case installations. additional information on class services can be obtained from: bellcore customer svs. 18005212673 2016995800 foreign calls 2016990936 fax the document number is: tanwt000030 title: avoice band data transmission interface generic requirementso figure 7 is a conceptual design of how the mc14lc5447 can be implemented into a product which will retrieve the in- coming message and convert it to eia232 levels for trans- mission to the serial port of a pc. with this message and appropriate software, the pc can be used to look up the name and any additional information associated with the call- er that had been previously stored. figure 8 is a conceptual design of an adjunct unit in paral- lel with an existing phone. this arrangement gives the sub- scriber cnd service without having to replace existing equipment. table 1. oscillator specifications clock select pin 11 = 1 crystal mode parallel frequency 3.579 mhz or 3.6864 mhz r f 10 m w c1 and c2 30 pf source: fox electronics 5570 enterprise pkwy. ft. myers, fl 33905 tel. 8136930099 clock select pin 11 = 0 resonator #csb455j frequency 455 khz 0.5% r f 1.0 m w c1 and c2 100 pf source: murata manufacturing co. ltd. 2200 lake park dr. smyma, ga 30080 tel. 4044361300 rf osc in c1 c2 osc out note: motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing. a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc14lc5447 motorola 6 design information the circuit in figure 2 illustrates in greater detail the rela- tionship between pins 3, 4, 6, and 7. the external component values shown in figure 2 are the same as those shown in figures 7 and 8. when v dd is applied to the circuit in these two figures, the rc network will charge cap c1 to v dd holding rt (pin 6) off. if the pwrup (pin 7) is also held at v dd , the mc14lc5447 will be in a powerdown mode, and will consume 1 m a of supply current (max). the resistor network (r2 r4) attenuates the incoming power ring applied to the top of r2. the values given have been chosen to provide a sufficient voltage at rdi1 (pin 3) to turn on the schmitttrigger input with approximately a 40 vrms or greater power ring input from tip and ring. when v t+ of the schmitt is exceeded, q1 will be driven to satura- tion discharging cap c1 on rt . this will initialize a partial powerup, with only the portions of the part involved with the ring signal analysis enabled, including rdi2 (pin 4). at this time the mc14lc5447 power consumption is increased to approximately 2.4 ma (typ). to bridge ring analysis circuit internal power up rt pwrup logic v ref 1.2 v external components internal components v dd 6 pwrup 7 rdi1 3 rdi2 4 r1 270 k w r3 18 k w r4 15 k w 470 k w r2 c1 0.2 m f q1 to rdo pin figure 2. the value of r1 and c1 must be chosen to hold the rt pin voltage below the v t+ of the rt schmitt between the individ- ual cycles of the power ring. the values shown will work for ring frequencies of 15.3 hz (min). with rdi2 now enabled, a portion of the power ring above 1.2 v is fed to the ring analysis circuit. this circuit is a digital integrator which looks at the duty cycle of the incoming sig- nal. when the input to rdi2 is above 1.2 v, the integrator is counting up at an 800 hz rate. when the input to rdi2 falls below 1.2 v, the integrator counts down at a 400 hz rate. 3.25 2.75 1.75 1.25 2.25 2.0 1.0 1.5 3.5 3.0 2.5 v dd 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v t v t+ figure 3. v dd versus v t+ and v t v t a ring is qualified when an internal count of binary 48 is reached. the ring is disqualified when the count drops to a binary 32. the number of ring cycles required to qualify the signal will depend on the amplitude of the voltage presented to rdi2. the shortest amount of time needed to do the quali- fication is approximately 60 ms. the shortest amount of time required for dequalification will be approximately 40 ms. once the ring signal is qualified, the rdo pin will be sent low. this can be fed back to pwrup as shown in figure 7, or with a pullup resistor, can be used as an interrupt to an mcu as shown in figure 8. in either case, once the pwrup pin is below v t , the part will be fully powered up, and ready to receive fsk. during this mode, the device current will in- crease to approximately 6.2 ma (typ). the state of the rt pin is now a adon't careo as far as the part is concerned. normal- ly, however, this pin will be allowed to return to v dd . after the fsk message has been received, the pwrup pin can be allowed to return to v dd and the part will return to the standby mode, consuming less than 1 m a of supply cur- rent. the part is now ready to repeat the same sequence for the next incoming message. typical demodulator performance the following describes the performance of the mc14lc5447 demodulator in the presence of noise over a simulated bell 3002 telephone loop. the bell 3002 loop represents a worst case local tele- phone loop in north america. the characteristics of this loop, which affect performance, are high frequency attenuation and envelope delay distortion (edd) or group delay. the minimum receiver sensitivity of the mc14lc5447 un- der these conditions is typically 45 dbm. the mc14lc5447 achieves a bit error rate (ber) of 1 10 5 at a signaltonoise ratio (snr) of 15 db in v.23 op- eration and at an snr of 18 db in bell 202 operation (see figures 4 and 5). all measurements in dbm are referenced to 600 w : 0 dbm = 0.7746 vrms. all measurements were taken using the mc145460evk evaluation board. a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc14lc5447 motorol a 7 electronic file not available for this figure. to view the complete document, order it from the literature center. figure 4. mc14lc5447 v.23 operation (typical ber vs snr) electronic file not available for this figure. to view the complete document, order it from the literature center. figure 5. mc14lc5447 bell 202 operation (typical ber vs snr) v dd rt n/c rdi2 rdi1 ri ti 1 2 3 4 5 6 7 pwrup osc in clksin rdo cdo dor doc 15 14 13 12 11 10 9 osc out v dd 16 v dd 8 30 pf 30 pf 3.579 mhz 500 pf 500 pf 0.1 m f 10 k w 10 k w 10 m w figure 6. fulltime power without ring detect tip ring a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc14lc5447 motorola 8 application circuit rt 6 nc 5 rdi1 3 ri 2 ti 1 rdi2 4 pwrup 7 12 rdo 13 cdo 14 dor 15 doc 11 clksin 10 osc in 9 osc out mc14lc5447 3.579 mhz 30 pf 10 m w v dd to pc to pc 16 8 0.1 m f mc145407 v dd tip ring 1n4004x4 500 pf 500 pf c4 c3 c1 c2 10 k w 10 k w 470 k w 18 k w 15 k w 270 k w 4.7 m w protection network 30 pf 0.2 m f +5 v +5 v 0.33 m f note: c1 and c2 0.2 m f required for line isolation. c1 through c4 are 250 v min, nonpolarized. figure 7. partial implementation of pc interface to tip and ring timing diagram for figure 7 doc data notes: 1. wired `or' rdo with cdo. 2. overlap of rdo edge with cdo edge to ensure part stays in pwrup determined by rc time constant on rdo , pwrup , and cdo pin. 3. part reverts to pwr on , on rising edge of rdo since there is no cdo . note 1 cdo 3.58 mhz, 3.6864, or 455 khz pwrup rdo rt dor second ring 0.5 sec 2 seconds ri osc data data note 1 note 2 2 seconds first ring 0.5 sec 0101 1 note 3 a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc14lc5447 motorol a 9 application circuit to phone display mcu interrupt v dd 0.1 m f 2 k w 2 k w 3.68 mhz v dd 270 k w 0.2 m f 470 k w 18 k w 15 k w tip ring c3 10 k w 10 k w 500 pf 500 pf c4 c1 0.2 m f c2 0.2 m f v dd rt 6 nc 5 rdi1 3 ri 2 ti 1 rdi2 4 pwrup 7 12 rdo 13 cdo 14 dor 15 doc 11 clksin 10 osc in 9 osc out 16 8 mc14lc5447 figure 8. adjunct box concept for calling number display 0.5 sec 2 seconds data first ring 0101 1 0.5 sec 2 seconds second ring note 1 note 1 note 2 interrupt for mcu doc cdo pwrup rdo rt dor ri osc data 3.58 mhz, 3.6864 mhz, or 455 khz data notes: 1. mcu must assert pwrup to mc14lc5447. 2. no data detected, mcu powers down the mc14lc5447. timing diagram for figure 8 a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc14lc5447 motorola 10 data word count 30 bytes/600 hz 01010101 data 04 15 16 21 512 555 1212 mo day hour minute number 144 bits max check sum message type word marks std ring/20 hz 2 s 0.5 s 0.5 s 495 ms 4 s 2 s 250 ms 70 ms 175 ms 8 bits 8 bits 8 bits figure 9. single message format parameter length word parameter type word parameter length word std ring/20 hz 0.5 s 2 s variable 4 s 0.5 s 2 s 30 bytes/600 hz 01010101 data marks 250 ms variable data 144 data bits check sum 8 bits data 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 70 ms 04 15 16 21 512 555 1212 mo day hour minute number calling name parameter type word message length word message type word figure 10. multiple message format a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc14lc5447 motorol a 11 package dimensions p suffix plastic dip case 64808 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 dw suffix sog package case 751g02 dim min max min max inches millimeters a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 8x g 14x d 16x seating plane t s a m 0.010 (0.25) b s t 16 9 8 1 f j r x 45 m c k a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc14lc5447 motorola 12 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 20912; phoenix, arizona 85036. 18004412447 or 6023035454 3142 tatsumi kotoku, tokyo 135, japan. 038135218315 asi a / p acifi c : m o torol a s e mi c ondu c tor s h .k . l td. ; 8 b t a i p in g i ndu s tria l p a r k , i 5 1 t i n g k o k r oad , t a i po , n. t . , hon g kong . 85226629298 mc14lc5447/d
? a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .

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